sipo
sipo is a simple serial in parallel out circuit using the 74164 SIPO IC and some other magic for start bit detection. The data also persists after each packet, which means that the serial port only has to send an update if something has changed.
Schematic
Schematic (image)
Schematic (gEDA schematic + symbols)
How it works
1 First, the data (from computer) is pumped in through a
4.7k resistor and inverted.
2 Then the data goes to the SIPO IC as well as the clock of the
J-K flip-flop.
3 When the first downwards slope (which will be the start bit)
hits the J-K flip-flop, the J-K flip-flop is set high.
4 The J-K flip-flop (inverted output line) then lowers the
reset line to the counter, and this action allows the counter
to start counting.
5 The counter then divides the 14.7456MHz signal down to
115200Hz.
6 This 115200Hz is then divided 8 times again, to determine
when all 8 bits have been sent over the serial line.
7 Once all 8 bits have been sent, one pulse at the fastest
divisible speed is sent to the J-K flip-flop reset pin.
8 The J-K flip-flop is now reset, and ready to repeat this
cycle again.